| Unit name | Design Verification |
|---|---|
| Unit code | COMSM0115 |
| Credit points | 10 |
| Level of study | M/7 |
| Teaching block(s) |
Teaching Block 1 (weeks 1 - 12) |
| Unit director | Professor. Eder |
| Open unit status | Not open |
| Pre-requisites |
COMS21101 |
| Co-requisites |
None |
| School/department | Department of Computer Science |
| Faculty | Faculty of Engineering |
This unit introduces students to theoretical and practical aspects of design verification with a focus on HDL chip design. It starts with an overview of all the various verification techniques and explores their limits. We then focus on two major topics: Testing and Property Checking. Testing covers the use of simulators and assertions during simulation, building a test bench, collecting and measuring coverage. Property Checking investigates how to generate properties from a specification, system considerations involving abstraction and decomposition and the use of higher-order properties. We employ practical property checking languages and study formal property checking tools. The course concludes with a series of lectures on design and verification flow and risk assessment, including how to devise an appropriate verification strategy, how to write a verification plan and how to decide when a design can be signed off.
A book that covers some of the course is:
Janick Bergeron Writing Testbenches: Functional Verification of HDL Models First Edition, Kluwer Academic Publishers, 2000, ISBN: 0-7923-7766-4 Second Edition, Kluwer Academic Publishers, 2003, ISBN: 1-4020-7401-8
In May 2005 a comprehensive textbook on Design Verification was published:
Bruce Wile, John Goss and Wolfgang Roesner Comprehensive Functional Verification Elsevier, 2005, ISBN: 0-12-751803-7
Both books are available in the QB library.
