| Unit name | Fault Tolerant Computing and VLSI Testing |
|---|---|
| Unit code | COMSM0125 |
| Credit points | 10 |
| Level of study | M/7 |
| Teaching block(s) |
Teaching Block 2 (weeks 13 - 24) |
| Unit director | Professor. Pradhan |
| Open unit status | Not open |
| Pre-requisites |
None |
| Co-requisites |
None |
| School/department | Department of Computer Science |
| Faculty | Faculty of Engineering |
Faults and Fault Modeling. System failures such as hardware defects, faults, noise, design errors, techniques for detecting manufacturing defects, design errors and faults. Combinational Logic Test Pattern Generation, Iddq Testing, microproccessor Testing, Memory Testing, Ad Hoc Design for Testablity, Various Design for Testability and Built-In Self-Test. Design methods to enhance reliability, availability and serviceabiltiy in microchips. Models for evaluating the effectiveness of design techniques in terms of reliabilty and availability improvements versus costs in chip area, system complexity and power dissipation. Microchip test techniques, including concurrent and on-line testing, On-chip self-test and self diagnosis. system-on-a-Chip testing.
Aims:
This unit seeks to acquaint you with various aspects of designing reliable and testable computer system design. Topics covered span issues at both micro-chip level as well as board and system level.
Lectures (20). A further 80 hours are set aside for coursework and private study.
Coursework 50%: details will be available later. Examination 50%.
